About EE conservatism in regards to software tools, this is mainly because we are highly restricted in what tools we can use by the platforms we have to design for. If you want to use a specific FPGA or a specific ASIC process, you have to use the tools that the FPGA vendor or ASIC foundry officially supports.
I totally agree and sympathize here. I've seen a few solutions that compile to VHDL or Verilog, as most platforms support one of those, to work around this.
That is what UC Berkeley's Chisel (https://chisel.eecs.berkeley.edu/) does, and it seems to be what CLaSH does as well. The issue is the same as in the various compile-to-JS languages. The additional level of indirection can make things difficult to debug (and heaven knows HDL code is hard to debug already).
Also, there is the issue of interfacing with third-party IP blocks or builtin FPGA hardware slices. You either have to stub these out in your high-level description or simulate using the generated HDL.
